Low threshold voltage pentacene OTFTs with La2O3 gate insulating layer using TSD
P. K. Saikia [a], U.J. Mahanta[c], P. Saikia*[a], B. Baishya[a], R Sarma[b] & D. Saikia [a,b,c],* Author for corresponding; e-mail address: puja.saik@gmail.com
Volume: Vol.39 No.2 (APRIL 2012)
Research Article
DOI:
Received: 7 November 2011, Revised: -, Accepted: 9 March 2012, Published: -
Citation: Saikia P.K., Mahanta U., Saikia P., Baishya B. and Saikia R.S.&.D., Low threshold voltage pentacene OTFTs with La2O3 gate insulating layer using TSD, Chiang Mai Journal of Science, 2012; 39(2): 263-269.
Abstract
Pentacene OTFTs are successfully fabricated using La2O3 gate insulator. Two step deposition (TSD) method is used to grow pentacene film over La2O3 insulator. The use of high dielectric constant (High-k) low leakage gate dielectric reduces the threshold voltage of the OTFTs bellow 2V. The fabricated OTFTs gives very low threshold voltage -1.8V and sub-threshold swing 0.3V/decade. The calculated ON-OFF ratio is 3x104 and mobility is 0.02cm2/V.s .