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Low threshold voltage pentacene OTFTs with La2O3 gate insulating layer using TSD
Paper Type  |
Contributed Paper |
Title |
Low threshold voltage pentacene OTFTs with La2O3 gate insulating layer using TSD |
Author |
P. K. Saikia [a], U.J. Mahanta[c], P. Saikia*[a], B. Baishya[a], R Sarma[b] & D. Saikia [a,b,c], |
Email |
puja.saik@gmail.com |
|
Abstract: Pentacene OTFTs are successfully fabricated using La2O3 gate insulator. Two step deposition (TSD) method is used to grow pentacene film over La2O3 insulator. The use of high dielectric constant (High-k) low leakage gate dielectric reduces the threshold voltage of the OTFTs bellow 2V. The fabricated OTFTs gives very low threshold voltage -1.8V and sub-threshold swing 0.3V/decade. The calculated ON-OFF ratio is 3x104 and mobility is 0.02cm2/V.s . |
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Start & End Page |
263 - 269 |
Received Date |
2011-11-07 |
Revised Date |
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Accepted Date |
2012-03-09 |
Full Text |
Download |
Keyword |
Pentacene, Organic Thin Film Transistors, Low operating voltage, Oxygen annealing La2O3, Two step deposition (TSD) method, 72.20Jv, 73.61.Ng, 73.40.Qv |
Volume |
Vol.39 No.2 (APRIL 2012) |
DOI |
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SDGs |
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