Chiang Mai Journal of Science, Faculty of Science, Chiang Mai University

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Paper Type	Contributed Paper
Title	Low threshold voltage pentacene OTFTs with La2O3 gate insulating layer using TSD
Author	P. K. Saikia [a], U.J. Mahanta[c], P. Saikia*[a], B. Baishya[a], R Sarma[b] & D. Saikia [a,b,c],
Email	puja.saik@gmail.com
Abstract: Pentacene OTFTs are successfully fabricated using La₂O₃ gate insulator. Two step deposition (TSD) method is used to grow pentacene film over La₂O₃ insulator. The use of high dielectric constant (High-k) low leakage gate dielectric reduces the threshold voltage of the OTFTs bellow 2V. The fabricated OTFTs gives very low threshold voltage -1.8V and sub-threshold swing 0.3V/decade. The calculated ON-OFF ratio is 3x10⁴and mobility is 0.02cm²/V.s .
Start & End Page	263 - 269
Received Date	2011-11-07
Revised Date
Accepted Date	2012-03-09
Full Text	Download
Keyword	Pentacene, Organic Thin Film Transistors, Low operating voltage, Oxygen annealing La2O3, Two step deposition (TSD) method, 72.20Jv, 73.61.Ng, 73.40.Qv
Volume	Vol.39 No.2 (APRIL 2012)
DOI
Citation	Saikia P.K., Mahanta U., Saikia P., Baishya B. and Saikia R.S.&.D., Low threshold voltage pentacene OTFTs with La2O3 gate insulating layer using TSD, Chiang Mai J. Sci., 2012; 39(2): 263-269.
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Low Threshold Voltage Pentacene OTFTs with O2 Annealed Pr2O3 Gate Insulating Layer
page: 653 - 657
Author:Prasanta Kumar Saikia, Puja Saikia, Ranjit Sarma and Dipok Saikia
Vol.38 No.4 (OCTOBER 2011) View: 554 Download:161

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